windows haters (repost for albert wagner)

Ian Molton spyro at
Sun Jun 2 15:13:34 PDT 2002

On Sun, 2 Jun 2002 15:28:50 -0600
Justin Knierim <jrknierim at> wrote:

> I am interested in learning some more about these other system types
> since until now I have never heard of ARM systems.  Are there PC's
> that even have ARM processors in them today?

Not by the 'common' definition of PC - 'machine wot runs winders'.

however there used to be a number of ARM based computers from a small UK
company called Acorn (they designed the BBC Micro, also).

Acorn needed a new CPU following their enormously successful 6502 based
BBC Micro range (at least 2 in EVERY school, and this was 20 years
ago!). They looked at all the 'off the shelf' CPUs (68k, the 16 bit 6502
(6802?), etc.) and decided they were all far too naff, and set
themselves up to design the ARM CPU (now used in 2/3 mobile phones and a
MASSIVE percentage of PDAs, and DOZENS of household / industrial
appliances (and even un-rad-shielded in space, so reliable and simple is
their design!).

Their first 'real' CPU was the ARM1, designed using their own custom
built 16 bit 6502 derivative, and it ran like the wind, even at 4MHz.

The ARM 1 never made it beyond evaluation 'coprocessor' boards for the
BBC micro which now sell on ebay for over 500UKP each, so rare are they.

The ARM 1 was such a RISC CPU that it didnt even have a multiply. Acorn
decided this was a mistake, and so the ARM2 was born. This was used in
the highly successful Archimedes range of computers, as was its
successor, the ARM3 - almost the same, but it had a 4Kbyte combined insn
and data cache.

Sometime between the ARM2 and 3, Acorn span ARM off into a seperate
company. ARM Ltd, which is the only remaining branch of the once
innovative british technology firm microsoft and the (moronic) UK
government killed (no, Im not bitter, really...). Acorns manegment could
have used a kicking or two, also, though, to be fair.

in later machines, the ARM6 and 7 were used, the main improvements then
being higher clockspeed and marginally better multiply, along with a 32
bit address space mode (the ARM1 was a 32 bit CPU from the start, just
with 26 bit addressing, which allowed the processor status flags and MMU
bits to be stored in the remaining 6 bits of the program counter (a 32
bit register).

the StrongARM was the last CPU used ion Acorns machines, running at
300MHz max, dissipating about 300mW of power, and with a superscalar
multiply and load/store architecture, coupled with split 16 Kbyte I and
D caches and a write buffer (so called 'harvard architecture').

XScale is the latest ARM based CPU, and ARM11 is 'comming RSN.

(oh, and arond the time the ARM6 was in development, there was a chip
calle dthe FPA10 which was a floating point co-processor for all ARMS
with a co-processor bus.)

The ARM has 16 registers, all 32 bit, in user mode. R15 is the Program
Counter, R14 is the 'link register' (return addesss for a
branch-with-link instruction is stored here), R13 is the stack pointer,
and all the others are free for use.

All registers behave as general purpose resisters, and you can do
anything you like with even R13, and R14. R15 is the only odd one out,
as most operations on it are meaningless.

branch tables are easy, though - 

r1 = switch value (0 - n)

add pc, pc, r1, lsl #2  pc = pc + (offset << 2)
bl  option_0
bl  option_1
bl  option_n

That should give you a taste for the BEAUTIFULLY crafted and totally
orthogonal ARM instruction set...

*free shifts on the second operand of all arithmentic and logic ops
*superscalar multi-cycle instructions (most take only 1 cycle, some 2,
and the occasional 3. loads take 2 setup + n bus/cache cycles, stores
are similar)
*ternary instructions (nice)
*FREE conditional execution (skipped insns take only 1 cycle, the
comaprison is free.

example of conditional execution:

add r1, r1, #1
cmp r1, #5
addle r1, r1, #4     <--- free condition check
subge r1, r5, r4 lsl #4   <---- free shift of r4

add 1 to r1
if r1 less than 5, add 4

on a machine without this, it would have involved a branch, ergo, a
pipeline stall, AND the shift wouldnt have been free either, something

add r1, r1, #1
cmp r1, #5
ble .less
lsl r4, #4
sub r1, r5, r4
b   .continue
.less add r1, r1, #4
.continue <blah blah>

7 instructions compared to 4 - almost twice as many! AND its less
efficient, pipeline trashing code...

Acorns machines ran RISC OS (and some can run linux (soon, all will, as
I am porting it to the Archimedes range :-)

>  Just curious.  Google did not show many results.  Thanks.

the latest ARM hardware to run RISC OS is really old, but Microdigital
are building a new machine 'Omega' which looks like it;ll be nice,
despite some oddball design choices...
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